There has been a need for display devices that consume even less power for use in battery operated, compact, portable devices. As typical display devices that meet such a need, liquid crystal and organic EL (electroluminescent) display devices are known in the art. Active matrix-type display devices using these display elements, display devices that typically use three-terminal thin film transistors (TFTs) as the switching elements, usually bring about gray scale display by controlling the brightness of the pixels with analog voltage or current. For example, in the case of a liquid crystal display device by the application of analog voltage and in the case of organic EL display device by the flow of analog current, the brightness of the display elements is varied, bringing about gray scale display.
FIG. 10 shows the construction of a prior art active matrix liquid crystal panel. A method of bringing about gray scale display in this panel is described later. Reference numeral 101 denotes an active matrix-type liquid crystal panel comprising signal lines S1 to Sn, scan lines G1 to Gm intersecting the signal lines, and switching elements located in the vicinity of the intersection points. Si denotes any given signal line, Gj any given scan line, and reference numeral 102 a switching element in the vicinity of the intersection point of these lines, the switching element in this case being an example of a commonly used three-terminal thin film transistor (TFT). Reference numeral 103 denotes a liquid crystal element. A counter electrode Vcom is formed on the side confronting a transistor 102. Reference numeral 104 denotes a storage capacitor for helping to sustain the capacitance component of the liquid crystal element 103 to prevent image degradation. It is usual for an additional electrode Vst on the other side of the storage capacitor to be commonly connected to the counter electrode Vcom. An intersection point 105 on the transistor side corresponds to a pixel electrode.
To explain operation of the device simply, the scan line Gj reaches a high potential one time in one frame period and turns on the transistor 102. The pixel electrode 105, in other words the liquid crystal capacitor 103 and the storage capacitor 104, is charged with respect to the counter electrode Vcom to the potential corresponding to that of the signal line Si at the time the transistor 102 is turned on. The scan line Gj then reaches a low potential and the transistor 102 is turned off, the potential charged to the pixel electrode being held for one frame period. While it is usual to drive liquid crystal by alternating current, it is also common to synchronize the counter electrode Vcom and common electrode Vst that is the storage capacity with the signal line Si and apply inverted pulse waveforms, whereby amplitudes to the signal line Si are reduced. Reference numeral 106 denotes a shift register and a latch on the signal side. The shift register/latch 106 sequentially samples image signals and performs serial to parallel conversion using a clock signal CKH and a start signal STH inputted from an external circuit. FIG. 10 shows an example in which a digital image signal is supplied; a plurality of bits of the image signal are converted into analog signals by a D/A converter circuit 107, and the current is amplified by an operational amplifier 108 and is applied to the signal lines S1 to Sn. The scanning side is made up of a shift register 109 and an output buffer 110 that sequentially scans the scan lines from top to bottom using a clock signal CKV and a start signal STV applied from an external circuit and drives the scan lines GI to Gm by pulse waveforms.
FIG. 11 is a set of waveform diagrams associated with each part. HD shows a horizontal synchronizing signal, a cycle thereof being a horizontal scanning period H and equivalent to the STH cycle and to the CKV cycle. The phases of these cycles may be changed slightly depending on panel characteristics and the like. An input signal is a digital image signal whose data changes according to the CKH cycle. FF1, FF2, and FF3 show sampling pulses of the shift register on the signal side. For example, in cases in which there are 4 bits and 16 gray scales, when data is represented using hexadecimal numbers, “0” in FF1, “7” in FF2, “F” in FF3 are sampled and latched. When this data is converted from digital to analog using latch pulse timing, the height of the pulse changes with respect to the counter electrode potential Vcom, and thus gray scale is realized. By performing counter-inversion, the voltage amplitude of the signal line can be about halved in the case of alternating current driving of liquid crystal, and thus this is generally carried out. It is to be noted that there has been disclosed capacitively coupled driving wherein the storage capacitor 104 of FIG. 10 is formed such that it overlaps with a pre-stage gate (Gj−1, though not shown in the figure), and pulse voltages are applied from the side of the pre-stage gate, the counter electrode potential being fixed, such that the voltage amplitude of the signal line is about halved, as is realized with counter-inversion (Japanese Unexamined Patent Application Publication No. H3-35218). The same advantageous results can be obtained with capacitively coupled driving wherein pulse voltages are applied to the storage capacitor independently of the gate, the storage capacitor 104 not overlapping the pre-stage gate (Japanese Patent Application H11-255228).
FIG. 12 shows the selection sequence of scan lines. Time is plotted on the horizontal axis and selection lines on the vertical axis. The smallest width on the time axis is a horizontal scanning period H and the number of display lines is 16. As is shown in FIG. 12, the scan lines are sequentially scanned as in the selection sequence 0→1→2→ . . . →15. Therefore, one frame is completed by 16H, at which time the writing of the next frame begins. Though omitted in FIG. 12, in practice it is possible to provide vertical blanking periods in addition to line selection periods in a frame period. It is to be noted that the horizontal scanning period H, equal to the HD cycle shown in FIG. 11, is such that the analog signal is written to a pixel within this period.
The construction of a prior art active matrix organic EL panel is shown in FIG. 13. Parts having functions corresponding to those of parts in the liquid crystal panel of FIG. 10 are accorded like reference numerals. Reference numeral 401 denotes an active matrix-type organic EL panel comprising signal lines S1 to Sn, scan lines G1 to Gm intersecting with the signal lines, and switching elements located in the vicinities of the intersection points. Si is any given signal line and Gj is any given scan line. Reference numerals 402 and 403 denote a first and a second switching element in the vicinity of the intersection point of these lines, each switching element being shown as a three-terminal thin film transistor (TFT). Reference numeral 404 denotes an auxiliary capacitor serving to maintain the voltage of the signal line Si applied to the gate electrode of the second transistor 403 via a first transistor 402. Reference numeral 405 shows the location of a pixel electrode connected to a power line Vs via a second transistor 403. Reference numeral 406 denotes an organic EL element formed between a pixel electrode 405 and a counter electrode Vcom. The organic EL element 406 emits light when current is flowed between the counter electrode Vcom and the power line Vs, and gray scale display is brought about by controlling this current. The operation of the row driver circuit and the column driver circuit is similar to that of the liquid crystal display device of FIG. 1; a scan line Gj is sequentially scanned, the first transistor 402 is turned on, and the analog voltage outputted from the signal line Si is written to the gate of the second transistor 403 and the auxiliary capacitor 404.
As is described above, in prior art active matrix liquid crystal panels and organic EL panels, gray scale display is brought about by the analog modulation of brightness. For this purpose, it has been necessary to provide a D/A converter circuit in the row driver circuit to supply an analog amount of voltage or current to the panel. However, in the stage following that of the D/A converter circuit, it has been necessary to provide an operational amplifier as a current buffer for charging and discharging the signal line capacity, which is the load. This is one cause of the increase in the power consumption of the driver circuit as a whole. This increase is explained in that the static current flows continually even at the time the operational amplifier is not charging or discharging the load and the number of operational amplifiers is as many as the total number of signal lines. Thus, the sum of the power consumption caused by the static current of the operational amplifiers increases and occupies a large proportion of the power consumption of the driver circuit as a whole.
In gray scale display of an active matrix organic EL panel, because brightness is controlled by the amount of current flowing to the organic EL elements, the panel display quality is very sensitive to variances in current-voltage characteristics of the pixel transistors. Therefore, in order to prevent degradation in image quality such as unevenness in brightness, it is necessary to make the transistor characteristics uniform across the whole panel.
As one method of solving these problems concerning power and image quality, a driving method is known wherein instead of using analog circuits such as D/A converters and operational amplifiers, gray scale display is brought about digitally by temporal modulation using only two values of fixed voltages. In the present invention this is referred to as the digital gray scale display method. With the digital gray scale display method, there is no power loss due to static current of the analog circuit and requirements on the variance of transistor characteristics for high image quality are not stringent.
FIG. 14 shows the construction of a prior art digital gray scale display method using a liquid crystal display device as the example. In comparison with FIG. 10, FIG. 14 has disposed an analog multiplexer for selecting one of two values of fixed voltages VH and VL, in other words a decoder 501 and an analog switch 502 in place of a D/A converter circuit and an operational amplifier. The decoder and the analog switch can be constructed using a very simple circuit with which there is almost no static power consumption. In the case of digital driving using organic EL also, a decoder and an analog switch are disposed in place of a D/A converter circuit and an operational amplifier as is shown in FIG. 5. Particularly when the digital gray scale display method is applied to organic EL, even if the current-voltage characteristics of the pixel transistors slightly vary, high quality images without unevenness in brightness can be provided supposing the current variation is controlled with respect to the two values of fixed voltages. It is to be noted that the scanning side is constructed using a shift register circuit for bringing about sequential scanning as is shown in FIG. 7 and the analog driving is the same as that of FIG. 10.
A method of bringing about gray scale display using two values of fixed voltages VH and VL is now explained with reference to FIG. 15. A frame period for displaying all of the pixels is divided into a plurality of sub-frame periods that are temporally weighted and by applying, in each of the sub-frame periods, VH or VL to the pixel electrode in the case of a liquid crystal display device and to the gate electrode of the second transistor in the case of an organic EL display device, temporal pulse width modulation is brought about. FIG. 15 shows an example in which there are two values of fixed voltages and the number of sub-frames corresponds to the number of input data bits, there being four bits of input data and four sub-frames. Sub-frames SF4 to SF1 are allocated accordingly the most significant bit (MSB) of input data to the least significant bit (LSB) of input data. Through the input data and the combination of the two values of fixed voltages VH and VL in the weighted sub-frames SF1 to SF4, 16 levels of gray scale display are brought about. For example, when the gray scale data is 11 in decimal, in other words “1011” in binary, in the sub-frame SF3, VL, which corresponds to “0,” is selected and in the sub-frames SF1, SF2, and SF4, VH, which corresponds to “1,” is selected. It is to be noted that VH may be made to correspond to “0” and VL with “1” in accordance with transmittance-voltage characteristics (T-V characteristics) of the liquid crystal elements and light-emitting-current characteristics of organic EL.
In the prior art digital gray scale display method, in order to have a construction such that the sub-frames are temporally weighted, it is necessary to select scan lines as is shown in FIG. 16. FIG. 16 shows a case in which the number of sub-frames is four and scan lines are simply sequentially scanned from top to bottom, the more significant the bit the longer the sub-frame period in order to realize sub-frames having temporal weightings of 1:2:4:8. The frame period in the case of sequential scanning by digital driving in this manner is given byL(1+2+4+ . . . +2N−1)×H=(2N−1)HLwhere N is the number of sub-frames, L is the number of display lines and H is the horizontal scanning period. As is understood from the above equation, as the number of sub-frames N increases, the sub-frame period exponentially lengthens due to the portion of the equation 2 to the Nth power. In particular, in the sub-frame period corresponding to the most significant bit (MSB), the hold times of the other lines during which writing is not carried out is greatly lengthened. Thus, the frame cycle is lengthened and changes in display intensity known as flicker arise. On the other hand, when the frame frequency is fixed, there has been the problem of an increase in horizontal scanning frequency, resulting in an increase in power.
Dynamic contouring, an image quality problem specific to the digital gray scale display method, is now described. FIG. 17 shows the principle of the generation of dynamic contouring. In a case in which there are two values of fixed voltages, the number of sub-frames is four, the ratio of the sub-frame hold times is 1:2:4:8, and there are 16 levels of gray scale display, moving display is assumed and the successive changes in brightness of any given pixel over two frames is examined. In order to simplify the explanation, in FIG. 17, sub-frames are selected in order from sub-frame SF4 corresponding to the temporally most significant bit. It is supposed that in a first frame, gray scale “7,” in other words “0111,” is displayed and in a second frame, a gray scale “8,” in other words “1000,” is displayed. Thus, over 2 frames, “01111000” is displayed. Although the pattern of emitted light is accumulated and temporally averaged by the human eye, with a frame frequency of approximately 60 Hz, the pattern of emitted light, “.1111 . . . ,” which should be perceived as a brightness of the intended “7” or “8,” is momentarily perceived as a brightness of gray scale “16.” Thus, a sudden change in the significant bit brings about dynamic contouring. In order to prevent this phenomenon, it is common practice to employ techniques wherein the number of sub-frames is increased to suppress sudden bit changes as much as possible. For example, as is shown in FIG. 18, a gray scale of 16 is appropriately chosen where the number of sub-frames is five and the ratio of sub-frame hold times is 1:2:4:4:4. In this case, the shift from gray scale “7” to gray scale “8” becomes smooth and dynamic contouring associated with this gray scale shift is reduced. Nonetheless, dynamic contouring arising with the shift from gray scale “3” to gray scale “4” remains. Supposing the number of sub-frames is again increased, dynamic contouring can be reduced yet further. In this way, it is necessary to increase the number of sub-frames in order to reduce dynamic contouring, resulting in a lengthening in the frame cycle, and supposing the frame frequency is fixed, an increase in the horizontal scanning frequency results. The consequent increase in power has been a problem.